1. Field of the Invention
The present invention relates to a level conversion circuit that converts a signal of low amplitude into a signal of high amplitude.
2. Description of the Related Art
The structure of transistors constituting a semiconductor integrated circuit is miniaturized every year in order to increase the degree of integration. Accordingly, a power supply voltage (an operating voltage) for driving the transistors tends to decrease. If the power supply voltage is lowered, the reliability of gate insulators of the transistors can be prevented from lowering. Further, the power supply voltage has a tendency to decrease so as to curtail power consumption.
Meanwhile, the interface specification of an external signal that is input and output to and from a semiconductor integrated circuit (or a semiconductor chip) need to be compatible with that of other semiconductor chips mounted in a system. For this reason, a power supply voltage of an internal circuit, such as a logic circuit formed within the semiconductor integrated circuit, is frequently different from that of an input/output circuit through which an external signal is input and output. In this case, in order to convert a high-level voltage that is output from the internal circuit to the input/output circuit into a high-level voltage that is dealt in the input/output circuit, a level conversion circuit (a level-up conversion circuit) is required.
The level conversion circuit is disclosed in, e.g., in Japanese Unexamined Patent Application Publication Nos. 11-195975 and 2003-338178. This kind of the level conversion circuit includes a pair of nMOS transistors each having the gate for receiving an input signal of low amplitude, and a latch that is composed of a pair of pMOS transistors connected to the drains of the nMOS transistors. The source of each of the pMOS transistors is applied with a high-level power supply voltage being a voltage of a high level and high amplitude. Further, an output signal having high amplitude is output from the drains of the pMOS transistors.
As described above, the power supply voltage applied to the internal circuit of the semiconductor integrated circuit has a tendency to decrease. Consequently, the high-level voltage of the input signal input to the level conversion circuit tends to be low. If the power supply voltage applied to the internal circuit becomes lower than a threshold voltage of the nMOS transistors that receive the input signal of the level conversion circuit, the on-current of the nMOS transistors become very low. As a result, a latch state of the pMOS transistors cannot vary. That is, if the power supply voltage applied to the internal circuit is low, the conventional level conversion circuit malfunctions, and thus cannot invert the output signal in response to variations of the input signal.